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this is information on a product in full production. october 2014 docid018837 rev 8 1/48 vnq7140aj-e quad channel high-side driver with multisense analog feedback for automotive applications datasheet - production data features ? general ? quad channel smart high-side driver with multisense analog feedback ? very low standby current ? compatible with 3 v and 5 v cmos outputs ? multisense diagnostic functions ? multiplexed analog feedback of: load current with high precision proportional current mirror, v cc supply voltage and t chip device temperature ? overload and short to ground (power limitation) indication ? thermal shutdown indication ? off-state open-load detection ? output short to v cc detection ? sense enable/disable ? protections ? undervoltage shutdown ? overvoltage clamp ? load current limitation ? self limiting of fast thermal transients ? configurable latch-off on overtemperature or power limitation with dedicated fault reset pin ? loss of ground and loss of v cc ? reverse battery with external components ? electrostatic discharge protection applications ? all types of automotive resistive, inductive and capacitive loads ? specially intended for automotive signal lamps (up to r10w or led real combinations) description the vnq7140aj-e is a quad channel high-side driver manufactured using st proprietary vipower ? technology and housed in powersso-16 package. the device is designed to drive 12 v automotive grounded loads through a 3 v and 5 v cmos-compatible interface, providing protection and diagnostics. the device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. a faultrst pin unlatches the output in case of fault or disables the latch-off functionality. a dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to v cc and off-state open-load. a sense enable pin allows off-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices max transient supply voltage v cc 40 v operating voltage range v cc 4 to 28 v typ. on-state resistance (per ch) r on 140 m current limitation (typ) i limh 12 a stand-by current (max) i stby 0.5 a gapgcft00327 powersso-16 www.st.com
contents vnq7140aj-e 2/48 docid018837 rev 8 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 main electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3 protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1 power limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 negative voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 31 4.1.1 diode (dgnd) in the ground line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 immunity against transient electrical disturbances . . . . . . . . . . . . . . . . . . 32 4.3 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 multisense - analog current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.1 principle of multisense signal generation . . . . . . . . . . . . . . . . . . . . . . . 35 4.4.2 t case and v cc monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.4.3 short to vcc and off-state open-load detection . . . . . . . . . . . . . . . . . 38 4.5 maximum demagnetization energy (v cc = 16 v) . . . . . . . . . . . . . . . . . . . 39 5 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 powersso-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2 powersso-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
docid018837 rev 8 3/48 vnq7140aj-e contents 3 7 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
list of tables vnq7140aj-e 4/48 docid018837 rev 8 list of tables table 1. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. switching (vcc = 13 v; -40c < t j < 150c, unless otherwise specified) . . . . . . . . . . . . . 11 table 7. logic inputs (7 v < v cc <28v; -40c docid018837 rev 8 5/48 vnq7140aj-e list of figures 5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. i out /i sense versus i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. current sense precision vs. i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. switching time and pulse skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. multisense timings (current sense mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. multisense timings (chip temperature and vcc sense mode) . . . . . . . . . . . . . . . . . . . . . . 20 figure 9. t dskon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. latch functionality - behavior in hard short circuit condition (t amb << t tsd ) . . . . . . . . . . . 23 figure 11. latch functionality - behavior in hard short circuit condition . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) 24 figure 13. standby mode activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. standby state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 17. i gnd(on) vs. i out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 18. logic input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19. logic input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20. high level logic input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 21. low level logic input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 22. logic input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23. faultrst input clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 24. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 25. on-state resistance vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 26. on-state resistance vs. v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 27. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 28. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 29. won vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 30. woff vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 31. i limh vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 32. off-state open-load voltage detection threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 33. v sense clamp vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 34. v senseh vs. t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 35. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 36. simplified internal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 37. multisense and diagnostic ? block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 38. multisense block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 39. analogue hsd ? open-load detection in off-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 40. open-load / short to vcc condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 41. gnd voltage shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 42. maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 43. powersso-16 on two-layers pcb (2s0p to jedec jesd 51-5) . . . . . . . . . . . . . . . . . . . . 40 figure 44. powersso-16 on four-layers pcb (2s2p to jedec jesd 51-7) . . . . . . . . . . . . . . . . . . . . 40 figure 45. powersso-16 r thj-amb vs pcb copper area in open box free air condition . . . . . . . . . . . . 41 figure 46. powersso-16 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 41 figure 47. thermal fitting model for powersso-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 48. powersso-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
block diagram and pin description vnq7140aj-e 6/48 docid018837 rev 8 1 block diagram and pin description figure 1. block diagram table 1. pin functions name function v cc battery connection. output 0,1,2,3 power output. gnd ground connection. must be reverse battery protected by an external diode / resistor network. input 0,1,2,3 voltage controlled input pin with hysteresis, compatible with 3 v and 5 v cmos outputs. it controls output switch state. multisense multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. sen active high compatible with 3 v and 5 v cmos outputs pin; it enables the multisense diagnostic pin. sel 0,1,2 active high compatible with 3 v and 5 v cmos outputs pin; they address the multisense multiplexer. faultrst active low compatible with 3 v and 5 v cmos outputs pin; it unlatches the output in case of fault; if kept low, sets the outputs in auto-restart mode. &kdqqho &kdqqho &+ &+ &kdqqho &rqwuro 'ldjqrvwlf &kdqqho 9 && 9 21 /lplwdwlrq &xuuhqw /lplwdwlrq 9 && 287 &odps ,qwhuqdovxsso\ &+ 287387 &+ 08; &xuuhqw 6hqvh *1' 8qghuyrowdjh vkxwgrzq 9 && *1' &odps )dxow 7 6kruwwr9 && 2shq/rdglq2)) 2yhuwhpshudwxuh 3rzhu/lplwdwlrq 7 9 6(16(+ ,1387 6(/ 6(/ 6(q 0xowlvhqvh )dxow567 ,1387 287387 9 && *dwh'ulyhu ,1387 ,1387 287387 287387 6(/ ("1($'5
docid018837 rev 8 7/48 vnq7140aj-e block diagram and pin description 47 figure 2. configuration diagram (top view) table 2. suggested connections for unused and not connected pins connection / pin multisense n.c. output input sen, selxfaultrst floating not allowed x (1) 1. x: do not care. xxx to ground through 1 k resistor xnot allowed through 15 k resistor through 15 k resistor ,1387 ,1387 6(/ ,1387 ,1387 287387 287387 6(/ 1& 6(/ 287387 287387 6(q 0xowl6hqvh )dxow567 *1' 7$% 9 && 3rzhu662 *$3*&)7
electrical specification vnq7140aj-e 8/48 docid018837 rev 8 2 electrical specification figure 3. current and voltage conventions note: v fn = v outn - v cc during reverse battery condition. 2.1 absolute maximum ratings stressing the device above the rating listed in ta ble 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to the conditions in table below for extended periods may affect device reliability. 6 ,1 287387 0xowl6hqvh )dxow567 6( q 6(/ ,1387 , ,1 , 6(/ , 6(q , )5 , *1' 9 6(16( 9 287 9 && 9 )q , 6 , 287 , 6(16( 9 && 9 6(/ 9 6(q 9 )5 *$3*&)7 table 3. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 38 v -v cc reverse dc supply voltage 0.3 v ccpk maximum transient supply voltage (iso 16750-2:2010 test b clamped to 40v; r l =4 ) 40 v v ccjs maximum jump start voltage for single pulse short circuit protection 28 v -i gnd dc reverse ground pin current 200 ma i out output 0,1,2,3 dc output current internally limited a -i out reverse dc output current 4 i in input 0,1,2,3 dc input current -1 to 10 ma i sen sen dc input current i sel sel 0,1,2 dc input current i fr faultrst dc input current v fr faultrst dc input voltage 7.5 v
docid018837 rev 8 9/48 vnq7140aj-e electrical specification 47 2.2 thermal data i sense multisense pin dc output current (v gnd =v cc and v sense <0v) 10 ma multisense pin dc output current in reverse (v cc < 0 v) -20 e max maximum switching energy (single pulse) (t demag =0.4ms; t jstart =150c) 10 mj v esd electrostatic discharge (jedec 22a-114f) ? input 0,1,2,3 ? multisense ? sen, sel 0,1,2 , faultrst ? output 0,1,2,3 ?v cc 4000 2000 4000 4000 4000 v v v v v v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 table 3. absolute maximum ratings (continued) symbol parameter value unit table 4. thermal data symbol parameter typ. value unit r thj-board thermal resistance junction-board (jedec jesd 51-5 / 51-8) (1)(2) 1. one channel on. 2. device mounted on four-layers 2s2p pcb. 7.7 c/w r thj-amb thermal resistance junction-ambient (jedec jesd 51-5) (1)(3) 3. device mounted on two-layers 2s0p pcb with 2 cm 2 heatsink copper trace. 61 r thj-amb thermal resistance junction-ambient (jedec jesd 51-7) (1)(2) 26.8
electrical specification vnq7140aj-e 10/48 docid018837 rev 8 2.3 main electrical characteristics 7v docid018837 rev 8 11/48 vnq7140aj-e electrical specification 47 table 6. switching (v cc = 13 v; -40c < t j < 150c, unless otherwise specified) symbol parameter test conditions min. typ. max. unit t d(on) (1) 1. see figure 6: switching time and pulse skew . turn-on delay time at t j =25c r l =13 10 70 120 s t d(off) (1) turn-off delay time at t j = 25c 10 40 100 (dv out /dt) on (1) turn-on voltage slope at t j =25c r l =13 0.1 0.29 0.7 v/s (dv out /dt) off (1) turn-off voltage slope at t j = 25c 0.1 0.35 0.7 w on switching energy losses at turn-on (t won ) r l =13 ? 0.15 0.2 (2) 2. parameter guaranteed by design and characteri zation; not subject to production test. mj w off switching energy losses at turn-off (t woff ) r l =13 ?0.10.18 (2) mj t skew (1) differential pulse skew (t phl - t plh )r l =13 -90 -40 10 s table 7. logic inputs (7 v < v cc < 28 v; -40c < t j <150c) symbol parameter test conditions min. typ. max. unit input 0,1,2,3 characteristics v il input low level voltage 0.9 v i il low level input current v in =0.9v 1 a v ih input high level voltage 2.1 v i ih high level input current v in =2.1v 10 a v i(hyst) input hysteresis voltage 0.2 v v icl input clamp voltage i in =1ma 5.3 7.2 v i in =-1ma -0.7 faultrst characteristics v frl input low level voltage 0.9 v i frl low level input current v in =0.9v 1 a v frh input high level voltage 2.1 v i frh high level input current v in =2.1v 10 a v fr(hyst) input hysteresis voltage 0.2 v v frcl input clamp voltage i in =1ma 5.3 7.5 v i in =-1ma -0.7 sel 0,1,2 characteristics (7 v < v cc <18v) v sell input low level voltage 0.9 v i sell low level input current v in =0.9v 1 a v selh input high level voltage 2.1 v i selh high level input current v in =2.1v 10 a
electrical specification vnq7140aj-e 12/48 docid018837 rev 8 v sel(hyst) input hysteresis voltage 0.2 v v selcl input clamp voltage i in =1ma 5.3 7.2 v i in =-1ma -0.7 sen characteristics (7 v < v cc <18v) v senl input low level voltage 0.9 v i senl low level input current v in =0.9v 1 a v senh input high level voltage 2.1 v i senh high level input current v in =2.1v 10 a v sen(hyst) input hysteresis voltage 0.2 v v sencl input clamp voltage i in =1ma 5.3 7.2 v i in =-1ma -0.7 table 8. protections (7 v < v cc <18v; -40c docid018837 rev 8 13/48 vnq7140aj-e electrical specification 47 table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) symbol parameter test conditions min. typ. max. unit v sense_cl multisense clamp voltage v sen =0v; i sense =1ma -17 -12 v v sen =0v; i sense =-1ma 7 current sense characteristics k ol i out /i sense i out = 0.01 a; v sense = 0.5 v; v sen =5v 330 dk cal /k cal (1)(2) current sense ratio drift at calibration point i out = 0.01 a to 0.025 a; i cal = 17.5 ma; v sense =0.5 v; v sen =5v -30 30 % k led i out /i sense i out = 0.025 a; v sense = 0.5 v; v sen =5v 330 580 830 dk led /k led (1)(2) current sense ratio drift i out = 0.025 a; v sense = 0.5 v; v sen =5v -25 25 % k 0 i out /i sense i out = 0.070 a; v sense = 0.5 v; v sen =5v 375 550 720 dk 0 /k 0 (1)(2) current sense ratio drift i out = 0.070 a; v sense = 0.5 v; v sen =5v -20 20 % k 1 i out /i sense i out = 0.15 a; v sense =4v; v sen =5v 365 520 675 dk 1 /k 1 (1)(2) current sense ratio drift i out = 0.15 a; v sense =4v; v sen =5v -15 15 % k 2 i out /i sense i out = 0.7 a; v sense =4v; v sen =5v 380 475 570 dk 2 /k 2 (1)(2) current sense ratio drift i out = 0.7 a; v sense =4v; v sen =5v -10 10 % k 3 i out /i sense i out = 2 a; v sense =4v; v sen =5v 420 470 520 dk 3 /k 3 (1)(2) current sense ratio drift i out = 2 a; v sense =4v; v sen =5v -5 5 %
electrical specification vnq7140aj-e 14/48 docid018837 rev 8 i sense 0 multisense leakage current multisense disabled: v sen =0v 00.5 a multisense disabled: -1 v < v sense <5v (1) -0.5 0.5 multisense enabled: v sen = 5 v all channels on; i outx = 0 a; ch x diagnostic selected: ? e.g. ch 0 : v in0,1,2,3 =5v; v sel0 =0v; v sel1,2 =0v; i out0 = 0 a; i out1,2,3 =1a 02 multisense enabled: v sen =5v; ch x off; ch x diagnostic selected: ? e.g. ch 0 : v in0 =0v; v in1,2,3 =0v; v sel0 =5v; v sel1,2 =0v; i out1,2,3 =1a 02 v out_msd (1) output voltage for multisense shutdown v sen =5v; r sense =2.7k ? e.g. ch 0 : v in0 =5v; v sel0,1,2 =0v; i out0 =1a 5v v sense_sat multisense saturation voltage v cc =7v; r sense =2.7k ? ; v sen =5v; v in0 =5v; v sel0,1,2 =0v; i out0 = 2 a; t j = 150c 5v i sense_sat (1) cs saturation current v cc =7v; v sense =4v; v in0 =5v; v sen =5v; v sel0,1,2 =0v; t j = 150c 4ma i out_sat (1) output saturation current v cc =7v; v sense =4v; v in0 =5v; v sen =5v; v sel0,1,2 =0v; t j = 150c 2.2 a off-state diagnostic v ol off-state open-load voltage detection threshold v sen =5v; ch x off; ch x diagnostic selected ? e.g: ch 0 v in0 =0v; v sel0,1,2 =0v 234 v i l(off2) off-state output sink current v in =0v; v out =v ol ; t j = -40c to 125c -100 -15 a table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
docid018837 rev 8 15/48 vnq7140aj-e electrical specification 47 t dstkon off-state diagnostic delay time from falling edge of input (see figure 9 ) v sen =5v; ch x on to off transition; ch x diagnostic selected: ? e.g: ch 0 v in0 = 5 v to 0 v; v sel0,1,2 =0v; v out0 =4v; i out0 =0a 100 350 700 s t d_ol_v settling time for valid off-state open load diagnostic indication from rising edge of sen v in0,1,2,3 =0v; v fr =0v; v sel0,1,2 =0v; v out0 =4v; v sen = 0 v to 5 v 60 s t d_vol off-state diagnostic delay time from rising edge of v out v sen =5v; ch x off; ch x diagnostic selected: ? e.g: ch 0 v in0 =0v; v sel0,1,2 =0v; v out0 =0v to 4v 530s chip temperature analog feedback v sense_tc multisense output voltage proportional to chip temperature all channels off v sen =5v; v sel0 =0v; v sel1,2 =5v; v in0,1,2,3 =0v; r sense =1k ? ; t j = -40c 2.325 2.41 2.495 v v sen =5v; v sel0 =0v; v sel1,2 =5v; v in0,1,2,3 =0v; r sense =1k ? ; t j = 25c 1.985 2.07 2.155 v v sen =5v; v sel0 =0v; v sel1,2 =5v; v in0,1,2,3 =0v; r sense =1k ? ; t j = 125c 1.435 1.52 1.605 v dv sense_tc /dt (1) temperature coefficient t j = -40 c to 150 c -5.5 mv/k transfer function v sense_tc (t) = v sense_tc (t 0 )+dv sense_tc /dt*(t-t 0 ) v cc supply voltage analog feedback v sense_vcc multisense output voltage proportional to v cc supply voltage v cc =13v; v sen =5v; v in0,1,2,3 =0v; v sel0,1,2 =5v; r sense =1k ? 3.16 3.23 3.3 v transfer function (3) v sense_vcc =v cc /4 table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
electrical specification vnq7140aj-e 16/48 docid018837 rev 8 fault diagnostic feedback (see table 10 ) v senseh multisense output voltage in fault condition v cc =13v; r sense =1k ? ? e.g: ch 0 in open load v in0 =0v; v sen =5v; v sel0,1,2 =0v; i out0 = 0 a; v out0 =4v 56.6v i senseh multisense output current in fault condition v cc =13v; v sense =5v 7 20 30 ma multisense timings (current sense mode - see figure 7 ) t dsense1h current sense settling time from rising edge of sen v in =5v; v sen = 0 v to 5 v; r sense =1k ? ; r l =13 60 s t dsense1l current sense disable delay time from falling edge of sen v in =5v; v sen = 0 v to 5 v; r sense =1k ? ; r l =13 ? 520s t dsense2h current sense settling time from rising edge of input v in = 0 v to 5 v; v sen =5v; r sense =1k ? ; r l =13 ? 100 250 s t dsense2h current sense settling time from rising edge of i out (dynamic response to a step change of i out ) v in =5v; v sen =5v; r sense =1k ? ; i sense = 90 % of i sensemax ; r l =13 ? 100 s t dsense2l current sense turn- off delay time from falling edge of input v in = 5 v to 0 v; v sen =5v; r sense =1k ? ; r l =13 ? 50 250 s multisense timings (chip temperature sense mode - see figure 8 ) t dsense3h v sense_tc settling time from rising edge of sen v sen = 0 v to 5 v; v sel0 =0v; v sel1,2 =5v; r sense =1k ? 60 s t dsense3l v sense_tc disable delay time from falling edge of sen v sen = 5 v to 0 v; v sel0 =0v; v sel1,2 =5v; r sense =1k ? 20 s multisense timings (v cc voltage sense mode - see figure 8 ) t dsense4h v sense_vcc settling time from rising edge of sen v sen = 0 v to 5 v; v sel0,1,2 =5v; r sense =1k ? 60 s t dsense4l v sense_vcc disable delay time from falling edge of sen v sen = 5 v to 0 v; v sel0,1,2 =5v; r sense =1k ? 20 s table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
docid018837 rev 8 17/48 vnq7140aj-e electrical specification 47 multisense timings (multiplexer transition times) (4) t d_xtoy multisense transition delay from ch x to ch y v in0 =5v; v in1 =5v; v sen =5v; v sel1,2 =0v; v sel0 = 0 v to 5 v; i out0 = 0 a; i out1 = 1a; r sense =1k ? 20 s t d_cstotc multisense transition delay from current sense to t c sense v in0 =5v; v sen =5v; v sel0,1 =0v; v sel2 = 0 v to 5 v; i out0 = 0.5 a; r sense =1k ? 60 s t d_tctocs multisense transition delay fromt c sense to current sense v in0 =5v; v sen =5v; v sel0,1 =0v; v sel2 = 5 v to 0 v; i out0 = 0.5 a; r sense =1k ? 20 s t d_cstovcc multisense transition delay from current sense to v cc sense v in3 =5v; v sen =5v; v sel0,1 =5v; v sel2 = 0 v to 5 v; i out3 = 0.5 a; r sense =1k ? 60 s t d_vcctocs multisense transition delay from v cc sense to current sense to v in3 =5v; v sen =5v; v sel0,1 =5v; v sel2 = 5 v to 0 v; i out3 = 0.5 a; r sense =1k ? 20 s t d_tctovcc multisense transition delay from t c sense to v cc sense v cc =13v; t j =125c; v sen =5v; v sel1,2 =5v; v sel0 = 0 v to 5 v; r sense =1k ? 20 s t d_vcctotc multisense transition delay from v cc sense to t c sense v cc =13v; t j =125c; v sen =5v; v sel1,2 =5v; v sel0 = 5 v to 0 v; r sense =1k ? 20 s t d_cstovsenseh multisense transition delay from stable current sense on ch x to v senseh on ch y v in0 =5v; v in1 =0v; v sen =5v; v sel1,2 =0v; v sel0 = 0 v to 5 v; i out0 = 1 a; v out1 =4v; r sense =1k ? 20 s 1. parameter specified by design; not subject to production test. 2. all values refer to v cc = 13 v; t j = 25c, unless otherwise specified. 3. v cc sensing and t c sensing are referred to gnd potential. 4. transition delays are measured up to +/- 10% of final conditions. table 9. multisense (7 v < v cc < 18 v; -40c < t j < 150c) (continued) symbol parameter test conditions min. typ. max. unit
electrical specification vnq7140aj-e 18/48 docid018837 rev 8 figure 4. i out /i sense versus i out figure 5. current sense precision vs. i out ? e ? ? ? docid018837 rev 8 19/48 vnq7140aj-e electrical specification 47 figure 6. switching time and pulse skew figure 7. multisense timings (current sense mode) 9287 w 9ff wzrq 9ff 9ff wzrii ,1387 wgrq ws/+ ws+/ wgrii w g9 287 gw 21 2)) g9 287 gw ("1($'5 &xuuhqw6hqvh ,1 6(q , 287 w '6(16(+ w '6(16(/ w '6(16(/ w '6(16(+ 6(/ 6(/ /rz +ljk /rz +ljk /rz +ljk 6(/ /rz +ljk ("1($'5
electrical specification vnq7140aj-e 20/48 docid018837 rev 8 figure 8. multisense timings (chip temperature and v cc sense mode) figure 9. t dskon - xowl6hqvh 6(q 9 && w '6(16(+ w '6(16(/ w '6(16(/ w '6(16(+ 6(/ 6(/ /rz +ljk /rz +ljk /rz +ljk 9 6(16( 9 6(16(b9&& 9 6(16( 9 6(16(b7& 9&&92/7$*(6(16(02'( &+,37(03(5$785(6(16(02'( 6(/ /rz +ljk *$3*&)7 7 '67.21 9 ,1387 9 287 0xowl6hqvh 9 287 !9 2/ *$3*&)7
docid018837 rev 8 21/48 vnq7140aj-e electrical specification 47 table 10. truth table mode conditions in x fr sen sel x out x multisense comments standby all logic inputs low lllll hi-z low quiescent current consumption normal nominal load connected; t j < 150c lx refer to table 11 l refer to table 11 hl h outputs configured for auto-restart hh h outputs configured for latch-off overload overload or short to gnd causing: t j >t tsd or t j > t j_sd lx refer to table 11 l refer to table 11 hl h output cycles with temperature hysteresis h h l output latches-off under- voltage v cc v usd + v usdhyst (rising) off-state diagnostics short to v cc lx refer to table 11 h refer to table 11 open-load l x h external pull-up negative output voltage inductive loads turn-off lx refer to table 11 <0v refer to table 11
electrical specification vnq7140aj-e 22/48 docid018837 rev 8 table 11. multisense multiplexer addressing sen sel 2 sel 1 sel 0 mux channel multisense output nomal mode overload off-state diag. (1) 1. in case the output channel corresponding to the selected mux channel is latched off while the relevant input is low, multisense pin delivers feedback according to off-state diagnostic. example 1: fr = 1; in 0 = 0; out 0 = l (latched); mux channel = channel 0 diagnostic; mutisense = 0 example 2: fr = 1; in 0 = 0; out 0 = latched, v out0 > v ol ; mux channel = channel 0 diagnostic; mutisense = v senseh negative output lxxx hi-z hlll channel 0 diagnostic i sense = 1/k * i out0 v sense = v senseh v sense = v senseh hi-z hllh channel 1 diagnostic i sense = 1/k * i out1 v sense = v senseh v sense = v senseh hi-z hlhl channel 2 diagnostic i sense = 1/k * i out2 v sense = v senseh v sense = v senseh hi-z hlhh channel 3 diagnostic i sense = 1/k * i out3 v sense = v senseh v sense = v senseh hi-z hhl lt chip sense v sense =v sense_tc hhlhv cc sense v sense =v sense_vcc hhhlt chip sense v sense =v sense_tc hhhhv cc sense v sense =v sense_vcc
docid018837 rev 8 23/48 vnq7140aj-e electrical specification 47 2.4 waveforms figure 10. latch functionality - behavior in hard short circuit condition (t amb << t tsd ) figure 11. latch functionality - beha vior in hard short circuit condition
electrical specification vnq7140aj-e 24/48 docid018837 rev 8 figure 12. latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) figure 13. standby mode activation
docid018837 rev 8 25/48 vnq7140aj-e electrical specification 47 figure 14. standby state diagram 1rupdo2shudwlrq 6wdqge\0rgh ,1[ /rz $1' )dxow567 /rz $1' 6(q /rz $1' 6(/[ /rz ,1[ +ljk 25 )dxow567 +ljk 25 6(q +ljk 25 6(/[ +ljk w!w 'b67%< *$3*&)7
electrical specification vnq7140aj-e 26/48 docid018837 rev 8 2.5 electrical characteristics curves figure 15. off-state output current figure 16. standby current figure 17. i gnd(on) vs. i out figure 18. logic input high level voltage figure 19. logic input low level voltage figure 20. high level logic input current 7>?&@ ,orii>q$@ *$3*5, 2ii6wdwh 9ff 9 9lq 9rxw 7>?&@ ,67%<>? $@ *$3*5, 9ff 9 7>?&@ ,*1'21>p$@ 9ff 9 ,rxw ,rxw $ *$3*5, 7>?&@ 9l+9)5+96(/+96(q+>9@ *$3*5, 7>?&@ 9lo/9)5/96(//96(q/>9@ *$3*5, 7>?&@ ,l+,)5+,6(/+,6(q+>?$@ *$3*5,
docid018837 rev 8 27/48 vnq7140aj-e electrical specification 47 figure 21. low level logic input current figure 22. logic input hysteresis voltage figure 23. faultrst input clamp voltage figure 24. undervoltage shutdown figure 25. on-state resistance vs. t case figure 26. on-state resistance vs. v cc 7>?&@ ,l/,)5/,6(//,6(q/>?$@ *$3*5, 7>?&@ 9 lk\vw9)5k\vw96(/k\vw96(qk\vw>9@ *$3*5, 7>?&@ 9 )5&/>9@ ,lq p$ *$3*5, ,lq p$ 7>?&@ 986'>9@ *$3*5, 7>?&@ 5 rq>p2kp@ ,rxw $ 9ff 9 *$3*5, 9ff>9@ 5rq>p2kp@ 7 ?& 7 ?& 7 ?& 7 ?&
electrical specification vnq7140aj-e 28/48 docid018837 rev 8 figure 27. turn-on voltage slope figure 28. turn-off voltage slope figure 29. won vs. t case figure 30. woff vs. t case figure 31. i limh vs. t case figure 32. off-state open-load voltage detection threshold 7>?&@ g9rxwgw2q>9?v@ 9ff 9 5o *$3*5, 7>?&@ g9rxwgw2ii>9?v@ 9ff 9 5o *$3*5, 7>?&@ :rq>p-@ *$3*5, 7>?&@ :rii>p-@ *$3*5, 7>?&@ ,olpk>$@ 9ff 9 *$3*5, 7>?&@ 92/>9@ *$3*5,
docid018837 rev 8 29/48 vnq7140aj-e electrical specification 47 figure 33. v sense clamp vs. t case figure 34. v senseh vs. t case 7>?&@ 96(16(b&/>9@ ,lq p$ ,lq p$ *$3*5, 7>?&@ 96(16(+>9@ *$3*5,
protections vnq7140aj-e 30/48 docid018837 rev 8 3 protections 3.1 power limitation the basic working principle of this protection consists of an indirect measurement of the junction temperature swing t j through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output mosfet as soon as t j exceeds the safety level of t j_sd . according to the voltage level on the faultrst pin, the output mosfet switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (faultrst = low) or remains off (faultrst = high). the protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 thermal shutdown in case the junction temperature of the device exceeds the maximum allowed threshold (typically 175c), it automatically switches off and the diagnostic indication is triggered. according to the voltage level on the faultrst pin, the device switches on again as soon as its junction temperature drops to t r (see ta ble 8 , faultrst = low) or remains off (faultrst = high). 3.3 current limitation the device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, i limh , by operating the output power mosfet in the active region. 3.4 negative voltage clamp in case the device drives inductive load, the output voltage reaches negative value during turn off. a negative voltage clamp structure limits the maximum negative voltage to a certain value, v demag (see tab le 8 ), allowing the inductor energy to be dissipated without damaging the device.
docid018837 rev 8 31/48 vnq7140aj-e application information 47 4 application information figure 35. application diagram 4.1 gnd protection network against reverse battery figure 36. simplified internal structure v dd out out out out adc in out gnd gnd gnd gnd logic output gnd faultr st input sen sel v cc multisense current mirror rprot rprot rprot rprot rprot +5v r gnd rsense d gnd cext gnd gnd dld 0&8 ,1387 6(q 0xowlvhqvh )dxow567 9ff 287387 *1' 5surw 5surw 5surw 5surw 'og 5vhqvh 9 5 *1' ' *1' *1' *$3*&)7
application information vnq7140aj-e 32/48 docid018837 rev 8 4.1.1 diode (d gnd ) in the ground line a resistor (typ. r gnd =4.7k ) should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the ground network produces a shift ( 600 mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. this shift does not vary if more than one hsd shares the same diode/resistor network. 4.2 immunity against transient electrical disturbances the immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the v cc pin, is tested in accordance with iso7637-2:2011 (e) and iso 16750-2:2010. the related function performance status classification is shown in tab le 12 . test pulses are applied directly to dut (device under test) both in on and off-state and in accordance to iso 7637-2:2011(e), chapter 4. the dut is intended as the present device only, without components and accessed through v cc and gnd terminals. status ii is defined in iso 7637-1 function performance status classification (fpsc) as follows: ?the function does not perform as designed during the test but returns automatically to normal operation after the test?. table 12. iso 7637-2 - electrical transient conduction along supply line test pulse 2011(e) test pulse severity level with status ii functional performance status minimum number of pulses or test time burst cycle / pulse repetition time pulse duration and pulse generator internal impedance level u s (1) 1. u s is the peak amplitude as defined for each test pulse in iso 7637-2:2011(e), chapter 5.6. min max 1 iii -112v 500 pulses 0,5 s 2ms, 10 2a iii +55v 500 pulses 0,2 s 5 s 50 s, 2 3a iv -220v 1h 90 ms 100 ms 0.1 s, 50 3b iv +150v 1h 90 ms 100 ms 0.1 s, 50 4 (2) 2. test pulse from iso 7637-2:2004(e). iv -7v 1 pulse 100ms, 0.01 load dump according to iso 16750-2:2010 te st b (3) 3. with 40 v external suppressor referred to ground (-40c < t j < 150c). 40v 5 pulse 1 min 400ms, 2
docid018837 rev 8 33/48 vnq7140aj-e application information 47 4.3 mcu i/os protection if a ground protection network is used and negative transients are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line both to prevent the microcontroller i/o pins to latch-up and to protect the hsd inputs. the value of these resistors is a compromise between the leakage current of microcontroller and the current required by the hsd i/os (input levels compatibility) with the latch-up limit of microcontroller i/os. equation 1 v ccpeak /i latchup r prot (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = -150 v; i latchup 20ma; v oh c 4.5v 7.5 k r prot 140 k . recommended values: r prot =15k 4.4 multisense - analog current sense diagnostic information on device and load status are provided by an analog output pin (multisense) delivering the following signals: ? current monitor: current mirror of channel output current ? v cc monitor: voltage propotional to v cc ? t case : voltage propotional to chip temperature those signals are routed through an analog multiplexer which is configured and controlled by means of selx and sen pins, according to the address map in table 11 .
application information vnq7140aj-e 34/48 docid018837 rev 8 figure 37. multisense and diagnostic ? block diagram sel 1 sen multisense r sense r prot to uc adc out current sense fault fault diagnostic v senseh mux temp v cc i sense i out k factor v cc monitor temp monitor current monitor gate driver vcc ? out clamp t vcc ? gnd clamp internal supply undervoltage shut-down von limitation current limitation power limitation overtemperature short to vcc open-load in off sel 0 control & diagnostic gnd vcc input faultrst
docid018837 rev 8 35/48 vnq7140aj-e application information 47 4.4.1 principle of multisense signal generation figure 38. multisense block diagram current monitor when current mode is selected in the multisense, this output is capable to provide: ? current mirror proportional to the load current in normal operation , delivering current proportional to the load according to known ratio named k ? diagnostics flag in fault conditions delivering fixed voltage v senseh the current delivered by the current sense circuit, i sense , can be easily converted to a voltage v sense by using an external sense resistor, r sense , allowing continuous load monitoring and abnormal condition detection. normal operation (channel on, no fault, sen active) while device is operating in normal conditions (no fault intervention), v sense calculation can be done using simple equations current provided by multisense output: i sense = i out /k voltage on r sense : v sense = r sense . i sense = r sense . i out /k ).054 9ff 287 7rx&$'& 5 3527 5 6(16( 0dlq026 6hqvh026 9edw0rqlwru 7hpshudwxuhprqlwru )dxow 08/7,6(16( 0xowlvhqvh6zlwfk%orfn &xuuhqwvhqvh *$3*&)7
application information vnq7140aj-e 36/48 docid018837 rev 8 where : ? v sense is voltage measurable on r sense resistor ? i sense is current provided from multisense pin in current output mode ? i out is current flowing through output ? k factor represent the ratio between powermos cells and sensemos cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between i out and i sense . failure flag indication in case of power limitation/overtemperature, the fault is indicated by the multisense pin which is switched to a ?current limited? voltage source, v senseh (see table 9 ). in any case, the current sourced by the multisense in this condition is limited to i senseh (see ta ble 9 ). the typical behavior in case of overload or hard short circuit is shown in figure 10 , figure 11 and figure 12 . figure 39. analogue hsd ? open-load detection in off-state n n n n n 9 5 *1' n 9edw 5vhqvh n 9 '' 287 287 287 287 $'& lq *1' 287 q) *1' *1' *1' *1' *1' *1' q) 9 &(;7 ' *1' q) 9 *1' 0lfurfrqwuroohu 287387 9edw 5sxooxs ([whuqdo 3xoo 8s vzlwfk /rjlf *1' )dxow567 ,1387 6(q 6(/ 9 && 0xowlvhqvh &x uuhqwpluuru 287387 *$3*&)7
docid018837 rev 8 37/48 vnq7140aj-e application information 47 figure 40. open-load / short to v cc condition 4.4.2 t case and v cc monitor in this case, multisense output operates in voltage mode and output level is referred to device gnd. care must be taken in case a gnd network protection is used, because of a voltage shift is generated between device gnd and the microcontroller input gnd reference. figure 41 shows link between v measured and real v sense signal. table 13. multisense pin levels in off-state condition output multisense sen open-load v out >v ol hi-z l v senseh h v out v ol hi-z l v senseh h nominal v out application information vnq7140aj-e 38/48 docid018837 rev 8 figure 41. gnd voltage shift v cc monitor battery monitoring channel provides v sense = v cc / 4. case temperature monitor case temperature monitor is capable to provide information about actual device temperature. since diode is used for temperature sensing, following equation describe link between temperature and output v sense level: v sense_tc (t) = v sense_tc (t 0 )+dv sense_tc /dt*(t-t 0 ) where dv sense_tc / dt ~ typically -5.5 mv/k (for temperature range (-40 o c to +150 o c). 4.4.3 short to v cc and off-state open-load detection short to v cc a short circuit between v cc and output is indicated by the relevant current sense pin set to v senseh during the device off-state. small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. off-state open-load with external circuitry detection of an open-load in off mode requires an external pull-up resistor r pu connecting the output to a positive supply voltage v pu . it is preferable v pu to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. r pu must be selected in order to ensure v out > v olmax in accordance with to following equation: equation 2 7rx&$'& 9 6(16( 9 3527 0xowlvhqvhyrowdjhprgh 9 6(16(+ 9 && prqlwru 7 &$6( prqlwru *1' 6(q 6(/ 287 9 && 0xowlvhqvh 6(/ ,1 )dxow567 5 3527 n ' *1' 5 6(16( 9 0($685(' 5 3527 9 %$7 q)9 '!0'#&4 r pu v pu 4 ? i l off2 () min @ 4v ----------------------------------------------- - <
docid018837 rev 8 39/48 vnq7140aj-e application information 47 4.5 maximum demagnetization energy (v cc =16v) figure 42. maximum turn off current versus inductance note: values are generated with r l =0 . in case of repetitive pulses, t jstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. c : t jstart = 125 c repetitive pulse a : t jstart = 150 c single pulse b : t jstart = 100 c repetitive pulse 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq 'hpdjqhwl]dwlrq w 9 ,1 , / *$3*&)7 ,$ /p+ 914$- 0d[lpxpwxuqriifxuuhqwyhuvxvlqgxfwdqfh 914$-6lqjoh3xovh 5hshwlwlyhsxovh7mvwduw ?& 5hshwlwlyhsxovh7mvwduw ?& " # $ ("1($'5
package and pcb thermal data vnq7140aj-e 40/48 docid018837 rev 8 5 package and pcb thermal data 5.1 powersso-16 thermal data figure 43. powersso-16 on two-layers pcb (2s0p to jedec jesd 51-5) figure 44. powersso-16 on four-layers pcb (2s2p to jedec jesd 51-7) table 14. pcb properties dimension value board finish thickness 1.6 mm +/- 10% board dimension 77 mm x 86 mm board material fr4 copper thickness (top and bottom layers) 0.070 mm copper thickness (inner layers) 0.035 mm thermal vias separation 1.2 mm thermal via diameter 0.3 mm +/- 0.08 mm copper thickness on vias 0.025 mm footprint dimension (top layer) 2.2 mm x 3.9 mm heatsink copper area dimension (bottom layer) footprint, 2 cm 2 or 8 cm 2 ("1($'5 5pq (/%qmbof 7 $$ qmbof #puupn ("1($'5
docid018837 rev 8 41/48 vnq7140aj-e package and pcb thermal data 47 figure 45. powersso-16 r thj-amb vs pcb copper area in open box free air condition figure 46. powersso-16 thermal impedance junction ambient single pulse equation 3: pulse calculation formula where = t p /t ("1($'5 57+mdpe 57+mdpe 57+mbdpe &: 3&%&xkhdwvlqnduhdfpa = 7+ &: 7lphv &x fp &x fp &x irrwsulqw /d\hu ("1($'5 z th r th z thtp 1 ? () + ? =
package and pcb thermal data vnq7140aj-e 42/48 docid018837 rev 8 figure 47. thermal fitting model for powersso-16 note: the fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. table 15. thermal parameters area/island (cm 2 )footprint 2 8 4l r1 = r7 = r9 = r11 (c/w) 4.8 r2 = r8 = r10 = r12 (c/w) 1.8 r3 (c/w) 8 8 8 5 r4 (c/w) 16 6 6 4 r5 (c/w) 30 20 10 3 r6 (c/w) 26 20 18 7 c1 = c7 = c9 = c11 (w.s/c) 0.0002 c2 = c8 = c10 = c12 (w.s/c) 0.005 c3 (w.s/c) 0.08 c4 (w.s/c) 0.2 0.3 0.3 0.4 c5 (w.s/c) 0.4 1 1 4 c6 (w.s/c) 3 5 7 18
docid018837 rev 8 43/48 vnq7140aj-e package information 47 6 package information 6.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 6.2 powersso-16 package information figure 48. powersso-16 package dimensions ("1($'5
package information vnq7140aj-e 44/48 docid018837 rev 8 table 16. powersso-16 mechanical data symbol millimeters min. typ. max. 0 8 10 25 15 35 15 a 1.70 a1 0.00 0.10 a2 1.10 1.60 b0.20 0.30 b1 0.20 0.25 0.28 c0.19 0.25 c1 0.19 0.20 0.23 d 4.90 bsc d1 3.60 4.20 e 0.50 bsc e 6.00 bsc e1 3.90 bsc e2 1.90 2.50 h0.25 0.50 l 0.40 0.60 0.85 l1 1.00 ref n16 r0.07 r1 0.07 s0.20 tolerance of form and position aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15
docid018837 rev 8 45/48 vnq7140aj-e order codes 47 7 order codes table 17. device summary package order codes tube tape and reel powersso-16 vnq7140aj-e VNQ7140AJTR-E
revision history vnq7140aj-e 46/48 docid018837 rev 8 8 revision history table 18. document revision history date revision changes 25-oct-2011 1 initial release. 04-jul-2012 2 updated table 1: pin functions updated figure 2: configuration diagram (top view) table 3: absolute maximum ratings : ?v ccpk , v ccjs : added rows ?i sense , v esd : updated values and parameters ?-v sense : removed row updated table 4: thermal data table 5: power section : ?v usdreset , i gnd(on) : added row ?v clamp , t d_stby , i s(on) : upadated value updated table 6: switching (vcc = 13 v; -40c < tj < 150c, unless otherwise specified) table 7: logic inputs (7 v < vcc < 28 v; -40c < tj < 150c) : ?v icl , v frcl , v selcl , v sencl : updated value table 8: protections (7 v < vcc < 18 v; -40c < tj < 150c) : ?t latch_rst : updated values ?v demag : updated test conditions and value ?v on : updated test conditions updated table 9: multisense (7 v < vcc < 18 v; - 40c < tj < 150c) updated figure 7: multisense timings (current sense mode) and figure 8: multisense timings (chip temperature and vcc sense mode) added figure 9: tdskon updated section 2.4: waveforms added chapter 3: protections and chapter 4: application information 18-oct-2012 3 table 5: power section : ?i gnd(on) : updated values updated table 6: switching (vcc = 13 v; -40c < tj < 150c, unless otherwise specified) table 9: multisense (7 v < vcc < 18 v; -40c < tj < 150c) : ?v sense_cl , k ol , k led , k 0 , dk 0 /k 0 , k 1 , dk 1 /k 1 , k 2 , dk 2 /k 2 , k 3 , dk 3 /k 3 , v senseh : updated values ?v sense_tc : updated parameter
docid018837 rev 8 47/48 vnq7140aj-e revision history 47 21-jun-2013 4 updated table 2: suggested connections for unused and not connected pins table 3: absolute maximum ratings : ?v ccpk : updated parameter ?-i out , i sense : updated value ?e max : updated parameter and value table 5: power section : ?v f : updated test conditions table 8: protections (7 v < vcc < 18 v; -40c < tj < 150c) : ?t hyst : added note table 9: multisense (7 v < vcc < 18 v; -40c < tj < 150c) : ?dk cal /k cal : added row ?k ol , k led , k 0 , k 1 , k 3 : updated values ?i sense_sat , i out_sat : added note ?v sense_tc : updated test conditions and values ?v sense_vcc : updated test conditions table 11: multisense multiplexer addressing ? updated negative output values removed following tables: table: electrical transient requirements (part 1/3) table: electrical transient requirements (part 2/3) table: electrical transient requirements (part 3/3) updated section 3.1: power limitation , section 3.2: thermal shutdown , section 3.4: negative voltage clamp and section 4.1.1: diode (dgnd) in the ground line removed section: load dump protection added section 4.2: immunity against transient electrical disturbances updated section 4.4.1: principle of multisense signal generation updated figure 39: analogue hsd ? open-load detection in off-state updated table 13: multisense pin levels in off-state updated figure 41: gnd voltage shift added section 4.5: maximum demagnetization energy (vcc = 16 v) updated chapter 5: package and pcb thermal data updated section 6.2: powersso-16 package information 18-jul-2013 5 updated table 4: thermal data updated table 6: switching (vcc = 13 v; -40c < tj < 150c, unless otherwise specified) added section 2.5: electrical characteristics curves 20-sep-2013 6 updated disclaimer. 09-jun-2014 7 updated section 6.2: powersso-16 package information 22-oct-2014 8 updated table 16: powersso-16 mechanical data table 18. document revision history (continued) date revision changes
vnq7140aj-e 48/48 docid018837 rev 8 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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